The New 5G Receiver Chip Set to Boost Wearables and IoT Devices

Researchers from MIT have designed a compact, low-power receiver chip for smaller 5G smart devices, promising to make them more efficient and functional.

The receiver shows great resilience to interference. This new chip is actually as much as thirty times more resilient to harmonic interference than some of the existing wireless receivers.

Additionally, the chip can enable devices to last longer by providing them with increased battery life. This makes the new receiver perfect for battery-powered Internet of Things (IoT) devices such as smart thermostats and environmental sensors, as well as smart cameras, industrial monitoring sensors, and wearables that are required to run for extended periods of time.

The key innovative design of the receiver, along with its passive filtering mechanism, allows devices to consume less than a milliwatt (one-thousandth of a watt) of static power. Not only does it conserve energy, but it also prevents device jamming by protecting both the input and output of the receiver’s amplifier from undesirable signals.

Yet another novel approach taken by researchers here involves a new arrangement of stacked capacitors that are precharged. These capacitors are also connected by a network of tiny switches that require significantly less power to turn on and off than the usual ones used in IoT receivers.

Both the amplifier and the capacitor network of the receiver are arranged carefully to take advantage of a phenomenon in amplification that allows the chip to use much smaller capacitors than is usually required.

This means smart devices like wearables and sensors can be made smaller while having longer battery lives, noted the paper’s lead author, Soroush Araei, who's an electrical engineering and computer science (EECS) graduate student at MIT.

Moreover, these devices will be more reliable in crowded radio environments like smart city networks or factory floors. Overall, the “receiver could help expand the capabilities of IoT gadgets,” said Araei.

The paper on the new receiver design, called “A Harmonic-Suppressing Gain-Boosted N-Path Receiver with Clock Bootstrapping for IoT Applications, was presented recently at the IEEE Radio Frequency Integrated Circuits Symposium.

Rethinking the Receiver

In an IoT device, a receiver serves the role of an intermediary between the device and its environment. 

The task of this component is to detect and amplify wireless signals transmitted by other devices or sensors, filter out any noise and interference, and then convert those signals into digital data for processing. So, receivers have a significant impact on the connectivity of the IoT device as well as its battery life.

When designing receivers, a key focus is on low-power operation and compact size. They need to be small and lightweight enough to fit various battery-powered IoT devices. Besides cost-effectiveness for broader adoption, receivers also need to be compatible with different communication standards and protocols and have high selectivity to filter out unwanted signals in crowded environments.

Typically, IoT receivers operate on fixed frequencies and utilize simple, inexpensive single-narrowband filters to suppress noise. While effective, they don’t really work with the ongoing technological advancements.

With the advent of fifth-generation (5G) cellular network technology, we are now getting faster speeds, lower latency, and increased capacity compared to its predecessor. 

By enabling reduced-capability devices that are both more energy-efficient and affordable, 5G is opening the doors for innovative IoT applications. What this means is that the next generation of IoT devices needs receivers with the capability to operate across a broad frequency range while being economical and energy-efficient, which is “extremely challenging.”

As Araei explained:

“Now we need to not only think about the power and cost of the receiver, but also flexibility to address numerous interferers that exist in the environment.”

This means engineers can’t depend on bulky off-chip filters, usually used in devices operating on a wide frequency range, in order to bring down the cost, size, and power consumption of an IoT device.

While a network of on-capacitors with the capability to filter unwanted signals offers a solution, they are susceptible to a special kind of noise called harmonic interference, which the team addressed a couple of years ago.

In their previous paper, published in 2023, MIT researchers laid the foundation for their novel receiver chip.

At the time, they built a switch-capacitor network to address the unwanted harmonic signals early in the receiver chain. The noise was filtered out before they were amplified and converted into digital bits for processing.

With signal interference slowing down device performance and draining batteries, the focus is on designing devices that can block unwanted signals efficiently, a task that is particularly challenging and further exacerbated by the widespread adoption of 5G networks and future generations of wireless communication systems already under development.

To remove the need for bulky and expensive filters to block a range of signals, the researchers developed a circuit architecture that blocks noise at the input without affecting its performance.

“We are interested in developing electronic circuits and systems that meet the demands of 5G and future generations of wireless communication systems.”

– Senior author Negar Reiskarimian, the X-Window Consortium Career Development Assistant Professor in EECS at the time

The receiver even blocked high-power interference without bringing more noise into signal processing. The chip achieved about forty times better performance at blocking harmonious interference than many wideband receivers, without needing any additional hardware or circuitry, making it easier to manufacture the chip at scale.

According to Reiskarimian, who’s also a core faculty member of the Microsystems Technology Laboratories:

“In designing our circuits, we look for inspirations from other domains, such as digital signal processing and applied electromagnetics. We believe in circuit elegance and simplicity and try to come up with multifunctional hardware that doesn’t require additional power and chip area.” 

The Engineering Elegance of the Chip

MIT researchers developed the receiver chip using a mixer-first architecture. Here, a radio frequency (RF) signal is converted to a lower-frequency signal upon being received by the device, before being passed on to the converter.

This allows for a wide frequency range coverage while filtering out noise that’s close to the operating frequency. However, mixer-first receivers are prone to harmonic interference.

Harmonic interference results from signals with frequencies higher than the operating frequency of the device. These frequencies can be hard to differentiate from the original signal when the time for conversion comes.

“A lot of other wideband receivers don’t do anything about the harmonics until it is time to see what the bits mean. They do it later in the chain, but this doesn’t work well if you have high-power signals at the harmonic frequencies. Instead, we want to remove harmonics as soon as possible to avoid losing information.”

– Araei 

So, what the team did was take block digital filtering and adapt it to the analog domain using capacitors.

Capacitors are charged up when the signal is received, and then they get switched off to hold that charge for data processing later.

These capacitors can be connected in many different ways. Connecting them in parallel is one way that enables these capacitors to exchange the stored charges, and while this can address harmonic interference, it ends up in the loss of signal. Another option is stacking capacitors, but on its own, it isn’t enough to provide resilience to harmonic interference.

The solution was arranging the capacitors in a very precise manner, which enabled the device to block harmonic interference but without any information loss.

Using charge sharing and capacitor stacking together wasn’t done before, until the team found it to be beneficial when done simultaneously. As Araei noted, they even “found out how to do this in a passive way within the mixer without using any additional hardware while maintaining signal integrity and keeping the costs down.”

Upon testing the device, which involved sending a desired signal and harmonic interference simultaneously, the researchers found their chip to be effective at blocking harmonic signals, with only a slight reduction in signal strength. 

The chip was actually able to handle signals that were 40 times more powerful than previous, advanced wideband receivers.

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Towards Scalable, Energy-harvesting 5G Devices

In the latest research from this month, the MIT researchers extended their approach. What they have done is use the switch-capacitor network as the feedback path in an amplifier with negative gain. This particular configuration takes advantage of the Miller effect.

Named after John Milton Miller, who first described it in 1920, the Miller effect describes the situation where the capacitance (the ability of an object to store electric charge) between the input and output of an amplifier (an electronic component that increases the strength of weak electrical signals) appears as a larger capacitance at the input. 

The effect allows small capacitors to behave like far bigger capacitors.

“This trick lets us meet the filtering requirement for narrow-band IoT without physically large components, which drastically shrinks the size of the circuit.”

– Araei 

The receiver designed by researchers has an active area of less than 0.05 square millimeters. There was one challenge that researchers had to overcome, and that was deciding just how to apply enough voltage to drive the switches while keeping the chip’s overall power supply low, at only 0.6 volts.

However, if the voltage needed for switching is too low, such tiny switches can turn on and off in error when there are interfering signals present. For this, a special circuit method was utilized by researchers.

The method called bootstrap clocking enhances the control voltage enough to make sure that the switches work accurately while consuming less power and fewer elements than conventional clock boosting techniques.

All the innovations together enable the new receiver to use power less than a milliwatt (mW) while blocking far more harmonic interference than conventional IoT receivers. According to Araei:

“Our chip also is very quiet, in terms of not polluting the airwaves. This comes from the fact that our switches are very small, so the amount of signal that can leak out of the antenna is also very small.” 

The prototype receiver (RX) is implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology, occupying 0.048 mm² and consuming power between the range of 1.27-5.48 mW. The receiver operates across a frequency range of 0.25-3 GHz and accomplishes blocker 1-dB compression point (B1dB) of -3/-2 dBm at the 3rd/5th harmonics, respectively. Local oscillator (LO) leakage at the antenna port also shows superior performance compared to state-of-the-art designs, with worst-case -73 dBm across the entire frequency range.

Due to being smaller in size than conventional devices, as well as relying on precharged capacitors and switches rather than more complex electronics, the receiver could be more cost-effective to fabricate. 

Also, with the design of the receiver being able to cover a wide range of signal frequencies, it can be implemented on a variety of existing and future IoT devices.

Supported in part by the National Science Foundation, the researchers have developed the prototype and now aim to enable their receiver to operate without a dedicated power supply. To power the chip, they can look into utilizing Bluetooth or Wi-Fi signals from the environment.

Investment in the Analog and Mixed-Signal Integrated Circuits Market

When it comes to investing in the sector, one of the most relevant companies to explore here is Analog Devices. A major player in analog and mixed-signal semiconductors, ADI develops data converters, amplifiers, radio frequency (RF) ICs, edge processors, power management, and other sensors. It also invests in energy-efficient architectures for wireless devices.

Analog Devices (ADI +2.13%) 

If we look at the market performance of ADI stocks, they are currently trading at $234.68, up 10.46% YTD. The company's stocks have actually been enjoying a positive market trend for more than a decade, with prices hitting an all-time high at nearly $244 earlier this year. Even after experiencing a tumble to almost $164 in April along with the broad market, it has since recovered nicely, recording a positive performance of about 42.5%.

With that, it has an EPS (TTM) of 3.67 and a P/E (TTM) of 64.03. A dividend yield of 1.69% is also offered by the company to its shareholders.

As for company financials, Analog Devices reported revenue of $2.64 billion for its fiscal second quarter of 2025, which ended May 3, 2025. With double-digit YoY growth recorded across all end markets, the company had $3.9 billion in operating cash flow and free cash flow of $3.3 billion on a trailing twelve-month basis.

“ADI delivered second quarter revenue and earnings per share above the high end of guidance,” said CEO Vincent Roche. “Against a backdrop of global trade volatility, our performance reflects the ongoing cyclical recovery, and the strength and resiliency of our business model. Our unwavering commitment to innovation and customer success, enables ADI to continue extending our leadership at the increasingly AI-driven Intelligent Edge, delivering exceptional value for shareholders over both the near- and long-terms.”

The improved demand recorded by Analog Devices this past quarter, according to CFO Richard Puccio, also supports their outlook for continued growth in the next quarter and reinforces their view “that we are in a cyclical upturn.”

For the third quarter of fiscal 2025, they are forecasting revenue of $2.75 billion and an operating margin of 27.2%. EPS is expected to be around $1.23.

During the second quarter, meanwhile, the company returned $0.7 billion to shareholders through dividends and repurchases. A quarterly cash dividend of $0.99 per share was also announced by the board, which will be paid on June 18, 2025.

This dividend reflects an 8% increase, announced in Feb. this year, which marked 21 consecutive years of higher dividends. At the same time, they got the authorization to repurchase an additional $10 billion of its common stock.

“ADI’s resilient business model and track record of delivering profitable growth enables our return of 100% of free cash flow to shareholders over the long term.”

– Roche

Meanwhile, this month, the company launched a corporate venture capital (CVC) fund called ADVentures (ADV) with an aim to invest in emerging opportunities that will define new frontiers in innovation and impact.

The focus will be on nascent ideas developing revolutionary solutions in Human Health, Advanced Systems & Robotics, and Climate & Energy, with particular interest in areas like AI, computing architectures, new sensing modalities, and secure connectivity.

In Jan. this year, Analog Devices also secured support from the U.S. Department of Commerce, which signed four non-binding contracts, per which it will provide up to $105 million in direct funding to the company. The contracts are part of the CHIPS and Science Act, designed to boost the domestic semiconductor industry.

Focused on enabling innovation at the Intelligent Edge, the investment will help it strengthen its workforce training and partnerships as well as manage its environmental footprint.

Latest Analog Devices (ADI) Stock News and Developments

Conclusion

With next-generation IoT devices to utilize 5G technology, receivers need to be capable of handling a wide range of frequencies with low power consumption and cost. 

Improved receiver technology here can lead to better connectivity, longer battery life, and more reliable performance for IoT devices, in turn, enabling a wider range of applications in areas like smart homes, industrial automation, healthcare, and environmental monitoring.

As demand for energy-efficient, interference-resilient receiver tech becomes critical, MIT’s compact, low-power receiver design can help smart devices achieve better performance and increased functionality, leading to smarter, smaller, and longer-lasting wearables and IoT devices for a truly interconnected world!

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